Download Low-Power High-Speed ADCs for Nanometer CMOS Integration by Zhiheng Cao, Shouli Yan PDF

By Zhiheng Cao, Shouli Yan

Low-Power High-Speed ADCs for Nanometer CMOS Integration is concerning the layout and implementation of ADC in nanometer CMOS methods that in achieving decrease strength intake for a given pace and backbone than past designs, via architectural and circuit thoughts that reap the benefits of specified good points of nanometer CMOS strategies. A part lock loop (PLL) clock multiplier has additionally been designed utilizing new circuit strategies and effectively established. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. utilizing offset canceling comparators and capacitor networks carried out with small price interconnect capacitors to interchange resistor ladder/multiplexer in traditional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz enter. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz inner clock in 130nm CMOS. a brand new form of structure that mixes flash and SAR allows the bottom energy intake, 6-bit >1GS/s ADC suggested up to now. This layout could be a drop-in substitute for latest flash ADCs because it does require any post-processing or calibration step and has a similar latency as flash. three) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for producing sampling clock to the SAR ADC. a brand new loop clear out constitution permits section mistakes preamplification to decrease PLL in-band noise with no expanding loop clear out capacitor dimension.

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We can see that due to finite hysteresis in the comparators that makes their offset dependent on previous decision, the settling is not perfect and it is only when the ADC input referred offset becomes about 1mV that the comparator makes decision to move the correction to the opposite direction. 1 LSB and will be random rather than limit-cycle-oscillation-like in the figure because the simulation does not consider thermal noise and other random noise. 25 GS/s 6 b 2 b/Step SAR ADC in 130 nm Digital CMOS Offset + quantization error Cp /Cs +1−z−1 Cp /Cs Vdd 8 DC offset free comparator output 1+z−1 2 Block diagram in each auto-zeroing phase Fig.

25 fF and a total capacitance of about 240 fF which is driven by the front-end T/H. The three capacitor networks occupy only 100 µm × 70 µm which is about 52% of the layout area. 2 Flip-Flop Bypass SAR Logic To achieve the 400 ps cycle time, delay of the SAR logic must be reduced so that as much as possible time can be allocated for c-net and quantizer preamp settling. 7 shows block and timing diagrams of a conventional successive approximation control logic, which consists of a shift register and an array of DFF forming the successive approximation register (SAR).

In theory more ADCs can be time-interleaved to obtain even higher sampling frequency [14]. However, offset, gain and sampling time mismatch create more tones and images of input signals, not to mention the increased area and input capacitance. The tones caused by offset mismatch among the channels are the largest error source, limiting the SNDR to 27 dB in [14]. These tones can be nulled by digitally adding offset until each channel’s output has equal averaged value. This, however, also removes any input signal components at these tone frequencies.

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