Download Design of Systems on a Chip: Design and Test by Ricardo Reis, Marcelo Soares Lubaszewski, Jochen A.G. Jess PDF

By Ricardo Reis, Marcelo Soares Lubaszewski, Jochen A.G. Jess

This publication is the second one of 2 volumes addressing the layout demanding situations linked to new generations of semiconductor know-how. many of the chapters are compiled from tutorials awarded at workshops lately via favourite authors from around the globe. expertise, productiveness and caliber are the most facets into consideration to set up the main standards for the layout and try out of upcoming structures on a chip.

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Extra resources for Design of Systems on a Chip: Design and Test

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This process occupies 64% of the processor capacity. 95 useful RISC operations per VLIW instruction. 9 operations per clock-cycle after correcting for cache misses and conflict stalls. The memory bus is loaded for 18% of its capacity. These are averages. Therefore under top load conditions degradation of the picture quality may occur. With the batman test series (500 frames) 44 of 36 CHAPTER 3 these frames present a load higher than 85% of the CPU capacity. This means that in fact for the DVD operation eventually an upgraded processor of the TRIMEDIA type with higher performance must be utilized.

The processor performs the MPEG2 decoding process of the “Digital Versatile Disk”-player (DVD-player) in real time with a clock period of 100 MHz. This process occupies 64% of the processor capacity. 95 useful RISC operations per VLIW instruction. 9 operations per clock-cycle after correcting for cache misses and conflict stalls. The memory bus is loaded for 18% of its capacity. These are averages. Therefore under top load conditions degradation of the picture quality may occur. With the batman test series (500 frames) 44 of 36 CHAPTER 3 these frames present a load higher than 85% of the CPU capacity.

The computations described so far all refer to the source encoding process, which compresses the bit-stream to be transmitted. In order to ensure reliable transmission CORE ARCHITECTURES FOR DIGITAL MEDIA 33 over the various channels more encoding is necessary which this time amounts to the addition of redundancy. Both Viterbi and Reed-Solomon encoding are applied. Also the technique of interleaving is applied. This technique implies the partition of the packets of a bit stream into equally sized blocks.

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