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Therefore the VBIC Early voltage parameters are derived from the f r SGP Early voltage parameters V AF and VAR by matching g o ⁄ I c and g o ⁄ Ie f f between the two models at specific values of forward bias, V be and V bc, r r and reverse bias, V bc and V be (McAndrew, 1996). From the SGP model 2 BTJ Modeling with VBIC Table 2. Mappings from SGP to VBIC parameters VBIC Mapping VBIC Mapping R M M C C JC RCX RCI O CJCP CJS RBX RBM PS VJS RBI RB - RBM MS MJS RE RE IBEI IS /BF IS IS NEI NF NF NF IBEN ISE NR NR NEN NE FC FC IBCI IS /BR CJE CJE NCI NR PE VJE IBCN ISC ME MJE NCN NC CJC RJCXCJC IKF IKF CJEP CJC (1 - XCJC) IKR IKR PC VJC TF TF 37 VBIC XTF VTF ITF TR TD EA EAIE EAIC EANE EANC XIS XII XIN KFN AFN Mapping XTF VTF ITF TR TF PTF /180 EG EG EG EG EG XTI XTI - XTB XTI - XTB KF AF are calculated, and then equation (44) is solved for VEF and VER.
7 V . The sensitivity of the gms / I D characteristic to a is found to be small. A suitable function is required to describe this characteristic; in the past, various analytical expressions of varying degree of accuracy have been used . A physics based expression has been proposed in , G(i f ) = 1 1 1 + if + 4 2 (12) derived from the assumption of a linear relationship between the surface potential s s and inversion charge density Qinv . This expression has the advantage of analytical simplicity.
This effect is accounted for in the VP (VG ) relation as described in , requiring two additional parameters. 4 Vertical field dependent mobility While oxide thickness is reduced when scaling CMOS technology, the power supply voltage is usually not reduced quite accordingly--as would be required by the constant field scaling--to maintain maximum speed for digital circuit applications. Thus higher fields result across the gate oxides in more advanced technologies . 3. A MOS Transistor Model for MixedAnalog-Digital Circuit Design 61 Table 1: Drain current in strong inversion.